Method for generation, placement, and routing of test...

Details Method for generation, placement, and routing of test... Method for generation, placement, and routing of test...

2007-05-31

2009-08-25

Chiang, Jack (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

07581202

ABSTRACT:
A method of generating and placing of test structures in test chips comprises creating a control data set for one or more device types, generating a test structure layout in response to the control data set, and placing the test structure layout within a given pad array layout of the at least one pad array as a function of a set of keywords. The control data set includes (i) a set of keywords and (ii) parameter geometries for corresponding ones of test structures associated with the set of keywords. The keywords each define at least (a) one or more pad allocations for each test structure of a given device type, (b) a number quantity of test structures for the given device type, and (c) placement information of the test structures relative to one or more pad allocations of at least one pad array. The pad array layout is configured for enabling a fabrication of corresponding test structures in test chips.

REFERENCES:
patent: 6658633 (2003-12-01), Devins et al.
patent: 7096446 (2006-08-01), Karniewicz
Kumar et al., “A Test Structure Adviosr and a Coupled, Library-Based Test Structure Layout and Testing Environment” IEEE Transactions on Semiconductor Manufacturing vol. 10, No. 3, Aug. 1997, pp. 370-383.
Kumar, M. V. et al.; “A Test Structure Advisor and a Coupled, Library-Based Test Structure Layout and Testing Environment”; IEEE Transactions on Semiconductor Manufacturing; Aug. 1997; pp. 370-383; vol. 10, No. 3; IEEE.

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