Programmable logic device integrated circuit with dynamic...

Details Programmable logic device integrated circuit with dynamic... Programmable logic device integrated circuit with dynamic...

2006-07-17

2009-06-30

Butler, Dennis M (Department: 2115)

Electrical computers and digital processing systems: support

Synchronization of clock or timing signals, data, or pulses

Using delay

C713S501000, C713S503000

Reexamination Certificate

active

07555667

ABSTRACT:
Adjustable transceiver circuitry is provided for programmable integrated circuits. The transceiver circuitry has a dynamic phase alignment circuit that can be used for aligning clock and data signals. The transceiver circuitry supports a phase-locked-loop source synchronous mode that can be used to receive data from transmitting integrated circuits that are clocked with a common clock. Each transmitting integrated circuit transmits a clock and associated data signals over a bus. The transceiver circuitry uses a master-slave architecture. A master dynamic phase alignment circuit in each transceiver receives the clock for that bus and selects a corresponding optimal clock phase to use in receiving input data for the bus from a multiphase clock. The master dynamic phase alignment circuit in each transceiver distributes the optimal clock phase to associated slave dynamic phase alignment circuits. Only a single phase-locked loop circuit is need to generate the multiphase clock.

REFERENCES:
patent: 6985096 (2006-01-01), Sasaki et al.
patent: 7003423 (2006-02-01), Kabani et al.
patent: 7034597 (2006-04-01), Mo et al.
patent: 7075365 (2006-07-01), Starr et al.
patent: 7340021 (2008-03-01), Churchill et al.
patent: 2001/0033188 (2001-10-01), Aung et al.
patent: 2004/0258410 (2004-12-01), Yajima et al.
patent: 2005/0117517 (2005-06-01), DeCusatis et al.
“Stratix II GX Transceiver Block Overview” Stratix II GX Device Handbook, vol. 2, pp. 1-1 to 1-8, Altera Corporation, Feb. 2006.
“Stratix II BX Physical Coding Sub-Layer”, pp. 1-3 printed from ww.altera.com on Mar. 21, 2006, Altera Corporation.
“Stratix II GX Transceiver FPGAs Physical Medium Attachment Layer”, pp. 1 and 2, printed from www.altera.com on Mar. 21, 2006, Altera Corporation.
“Source Synchronous Signaling in Stratix II Devices”, pp. 1 and 2, printed from www.altera.com on Mar. 21, 2006, Altera Corporation.

Affiliated with

Also associated with

Rating

Programmable logic device integrated circuit with dynamic... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Programmable logic device integrated circuit with dynamic..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Programmable logic device integrated circuit with dynamic... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4125819