Low power scan process with connected stimulus and scan paths

Details Low power scan process with connected stimulus and scan paths Low power scan process with connected stimulus and scan paths

2006-09-27

2009-02-17

Britt, Cynthia (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

Reexamination Certificate

active

07493538

ABSTRACT:
Scan architectures are commonly used to test digital circuitry in integrated circuits. The present invention describes a method of adapting conventional scan architectures into a low power scan architecture. The low power scan architecture maintains the test time of conventional scan architectures, while requiring significantly less operational power than conventional scan architectures. The low power scan architecture is advantageous to IC/die manufacturers since it allows a larger number of circuits (such as DSP or CPU core circuits) embedded in an IC/die to be tested in parallel without consuming too much power within the IC/die. Since the low power scan architecture reduces test power consumption, it is possible to simultaneously test more die on a wafer than previously possible using conventional scan architectures. This allows wafer test times to be reduced which reduces the manufacturing cost of each die on the wafer.

REFERENCES:
patent: 6158032 (2000-12-01), Currier et al.
patent: 6316959 (2001-11-01), Onodera
patent: 6327685 (2001-12-01), Koprowski et al.
patent: 6594802 (2003-07-01), Ricchetti et al.
“Two Techniques for Minimizing Power Dissipation in Scan Circuits During Test Applications” by Chakravarty et al. IEEE 1994.

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