Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2003-12-08
2009-02-03
Prenty, Mark (Department: 2822)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S272000
Reexamination Certificate
active
07485534
ABSTRACT:
A method of making a trench MOSFET includes forming a layer of porous silicon (26) at the bottom of a trench and then oxidizing the layer of porous silicon (26) to form a plug (30) at the bottom of the trench. This forms a thick oxide plug at the bottom of the trench thereby reducing capacitance between gate and drain.
REFERENCES:
patent: 4028149 (1977-06-01), Deines et al.
patent: 4104090 (1978-08-01), Pogge
patent: 4459181 (1984-07-01), Benjamin
patent: 4541001 (1985-09-01), Schutten et al.
patent: 4612465 (1986-09-01), Schutten et al.
patent: 4643804 (1987-02-01), Lynch et al.
patent: 4992390 (1991-02-01), Chang
patent: 5164325 (1992-11-01), Cogan et al.
patent: 6198127 (2001-03-01), Kocon
patent: 6331467 (2001-12-01), Brown et al.
patent: 6444528 (2002-09-01), Murphy
patent: 6809375 (2004-10-01), Takemori et al.
patent: 0205639 (1986-12-01), None
patent: WO 0072372 (2000-11-01), None
NXP B.V.
Prenty Mark
Zawilski Peter
LandOfFree
Method of manufacture of a trench-gate semiconductor device does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of manufacture of a trench-gate semiconductor device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of manufacture of a trench-gate semiconductor device will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4100906