Method and system for clock skew independent scan register...

Details Method and system for clock skew independent scan register... Method and system for clock skew independent scan register...

2005-03-16

2009-11-03

Tabone, Jr., John J (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S726000, C714S731000, C327S202000

Reexamination Certificate

active

07613969

ABSTRACT:
A method and system for clock skew independent scan chains. In one embodiment, a method comprises connecting a plurality of mux-D scan registers in a chain configuration, wherein a first mux-D scan register of the plurality is associated with a first clock network, and a second mux-D scan register of the plurality is associated with a second clock network. The plurality of mux-D scan registers have a scan mode. The first mux-D scan register and the second mux-D scan register become clock skew independent by controlling a scan-enable signal and a clock signal.

REFERENCES:
patent: 6060924 (2000-05-01), Sugano
patent: 6806731 (2004-10-01), Kohno
patent: 7038494 (2006-05-01), Morton
patent: 2005/0005214 (2005-01-01), Ueda
Digital Systems Testing and Testable Design; Copyright 1990; IEEE; Miron Abramovici, Melvin Breuer and Arthur Friedman; pp. 364-381.

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