SOI bottom pre-doping merged e-SiGe for poly height reduction

Details SOI bottom pre-doping merged e-SiGe for poly height reduction SOI bottom pre-doping merged e-SiGe for poly height reduction

2005-04-18

2009-10-20

Coleman, W. David (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C257SE21431

Reexamination Certificate

active

07605042

ABSTRACT:
Semiconductor device structures, and methods for making such structures, are described that provide for fully-doped transistor source/drain regions while reducing or even avoiding boron penetration into the transistor channel, thereby improving the performance of the transistor. In addition, such a transistor may benefit from an SiGe layer that applies compressive stress to the transistor channel, thereby further improving the performance of the transistor.

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P.R. Chidambaram, B., et al., “35% Drive Current Improvement from Recessed-SiGe Drain Extensions on 37 nm Gate Length PMOS”, 2004 Symposium on VLSI Technology, Digest of Technical Papers, pp. 48-49.
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Taiwanese Office Action for TW095111288 dated Feb. 22, 2008 and English Translation.

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