Method for extending lifetime reliability of digital logic...

Details Method for extending lifetime reliability of digital logic... Method for extending lifetime reliability of digital logic...

2008-05-20

2009-02-10

Tan, Vibol (Department: 2819)

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Signal level or switching threshold stabilization

C326S034000, C326S095000, C326S098000, C327S537000, C327S534000

Reexamination Certificate

active

07489161

ABSTRACT:
A method for extending lifetime reliability of CMOS circuitry includes coupling a first switching device between a logic high supply rail/logic low supply rail, and coupling a virtual supply rail to the CMOS circuitry. In a first mode of operation the first switching device supplies the full voltage value between the logic high supply rail and the logic low supply rail, and in a second mode of operation, the first switching device isolates the virtual supply rail from the logic high supply rail/logic low supply rail, thereby reducing the voltage supplied to the CMOS circuitry. A second switching device is coupled between the virtual supply rail and the logic low supply rail/logic high supply rail, wherein in a third mode of operation, the voltage on the virtual supply rail and the logic low supply rail/logic high supply rail is equalized.

REFERENCES:
patent: 6329874 (2001-12-01), Ye et al.
patent: 7145383 (2006-12-01), Mizuno et al.
patent: 7262631 (2007-08-01), Chong
patent: 7271615 (2007-09-01), Afghahi et al.
Chung-Hsien Hua et al.; “A Power Gating Structure with Concurrent Data Retention and Intermediate Modes in 100NM CMOS Technology;” 15th VLSI Design/CAD Symposium 2004.

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