Semiconductor memory device that can read out data at high speed

Details Semiconductor memory device that can read out data at high speed Semiconductor memory device that can read out data at high speed

1997-11-25

1999-05-25

Mai, Son

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

326 58, 326 83, G11C 700

Patent

active

059075090

ABSTRACT:
A .phi..sub.C generation circuit provides a column address buffer control signal to a column address buffer so that the column address buffer maintains a latch operation during the operation period of a differential amplifier. The column address buffer responds to a column address buffer control signal to latch an input address signal for providing a column address signal to a .phi..sub.D and PAE generation circuit. The .phi..sub.D and PAE generation circuit provides a differential amplifier activation signal to the differential amplifier according to a column address signal and a column access activation signal. The differential amplifier responds to a differential amplifier activation signal for amplifying data applied from a data input and output line to provide the same to a selector via a readout data line.

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patent: 5608688 (1997-03-01), Park
patent: 5623447 (1997-04-01), Shimoda
patent: 5640352 (1997-06-01), Honda
Toshiba Review, 1993, S. Sugiura et al., vol. 48, No. 12, pp. 915-918.

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