Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2007-10-18
2008-12-30
Pham, Thanh V (Department: 2894)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S218000, C438S508000, C257SE21632
Reexamination Certificate
active
07470582
ABSTRACT:
In formation of a source/drain region of an NMOS transistor, a gate-directional extension region <41a> of an N+block region <41> in an N+block resist film <51> prevents a well region <11> located under the gate-directional extension region <41a> from implantation of an N-type impurity. A high resistance forming region, which is the well region <11> having a possibility for implantation of an N-type impurity on a longitudinal extension of a gate electrode <9>, can be formed as a high resistance forming region <A2> narrower than a conventional high resistance forming region <A1>. Thus, a semiconductor device having a partially isolated body fixed SOI structure capable of reducing body resistance and a method of manufacturing the same are obtained.
REFERENCES:
patent: 5767549 (1998-06-01), Chen et al.
patent: 6410369 (2002-06-01), Flaker et al.
patent: 6441436 (2002-08-01), Wu et al.
patent: 6455894 (2002-09-01), Matsumoto et al.
patent: 6483165 (2002-11-01), Ooishi et al.
patent: 6495898 (2002-12-01), Iwamatsu et al.
patent: 2002/0072155 (2002-06-01), Liu et al.
patent: 2002/0110989 (2002-08-01), Hamaguchi et al.
patent: 2005/0037524 (2005-02-01), Matsumoto et al.
patent: 199 62 053 (2000-07-01), None
U.S. Appl. No. 09/466,934, filed Dec. 20, 1999, Yamaguchi et al.
Hirano, et al.,“Bulk-Layout-Compatible 0.18 μm SOI-COS Technology Using Body-Fixed Partial Trench Isolation (PTI)” Proceedings of 1999 IEEE International SOI Conference, Oct. 1999, pp. 131-132.
Maeda, et al.,“Analysis of Delay Time Instability According to the Operating Frequency in Field Shield Isolated SOI Circuits” Proceeding of IEEE Transactions of Electron Devices, vol. 45, No. 7, Jul. 1998, pp. 1479-1486.
Widmann, D., et al., “Technologie hichintegrierter Schaltungen”, Springer Verlag (1996), pp. 68-71.
Ipposhi Takashi
Iwamatsu Toshiaki
Maeda Shigenobu
McDermott Will & Emery LLP
Pham Thanh V
Renesas Technology Corp.
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