Dielectric relaxation memory

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Reexamination Certificate

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C365S149000, C365S185180, C257S302000, C257S330000

Reexamination Certificate

active

07457184

ABSTRACT:
A capacitor structure having a dielectric layer disposed between two conductive electrodes, wherein the dielectric layer contains at least one charge trap site corresponding to a specific energy state. The energy states may be used to distinguish memory states for the capacitor structure, allowing the invention to be used as a memory device. A method of forming the trap cites involves an atomic layer deposition of a material at pre-determined areas in the dielectric layer.

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