Method of creating core-tile-switch mapping architecture in...

Details Method of creating core-tile-switch mapping architecture in... Method of creating core-tile-switch mapping architecture in...

2005-10-11

2008-12-02

Do, Thuan (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

07461361

ABSTRACT:
There are provided a method of creating an optimized core-tile-switch mapping architecture in an on-chip bus and a computer-readable recording medium for recording the method. The core-tile-switch mapping architecture creating method includes: creating a core communication graph representing the connection relationship between arbitrary cores; creating a Network-on-chip (NOC) architecture including a plurality of switches, a plurality of tiles, and a plurality of links interconnecting the plurality of switches; and mapping the cores to the tiles using a predetermined optimized mapping method to thereby create the optimized core-tile-switch mapping architecture. The optimized mapping method includes first, second, and third calculating steps. According to the optimized core-tile-switch mapping architecture creating method and the computer-readable recording medium for recording the method, since the hop distance between cores is minimized, it is possible to minimize energy consumption and communication delay time in an on-chip bus. Furthermore, the optimized mapping architecture presents a standard for comparing the optimization of other mapping architectures.

REFERENCES:
patent: 5974487 (1999-10-01), Hartmann
patent: 7000212 (2006-02-01), Agrawal et al.
patent: 2004/0157569 (2004-08-01), Carballo et al.
patent: 1020030095083 (2003-12-01), None
Kumar et al., “A Network on Chip Architecture and Design Methodology,” Proceedings of the IEEE Computer Society Annual Symposium on VLSI (2002), 8 pages.

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