Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2006-07-06
2008-10-28
Chaudhari, Chandra (Department: 2891)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C257SE21415
Reexamination Certificate
active
07442612
ABSTRACT:
A double-gate field effect transistor (DGFET) structure and method of forming such a structure in which the parasitic capacitance under the source/drain regions is substantially reduced are provided. In the present invention, self-aligned isolation regions are provided to reduce the parasitic capacitance in the DGFET structure. Additionally, the present invention encapsulates the silicon-containing channel layer to enable the back-gate to be oxidized to a greater extent thereby reducing the parasitic capacitance of the structure even further.
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Chan Kevin K.
Hanafi Hussein I.
Solomon Paul M.
Chaudhari Chandra
International Business Machines - Corporation
Scully , Scott, Murphy & Presser, P.C.
Tuchman, Esq. Ido
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