Method for evaluating storage cell design using a wordline...

Static information storage and retrieval – Read/write circuit – Testing

Reexamination Certificate

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C365S194000, C714S718000

Reexamination Certificate

active

07414904

ABSTRACT:
A method for storage cell design evaluation provides accurate information about state changes in static storage cells. A wordline select pulse is propagated along the wordline select path of the test row to an output driver circuit, in order to test the clock and/or address timing of the row, so that variation of access timing, read stability and writeability with wordline strength/access voltage can be determined. An access detection cell holds the input of the output driver circuit until a simulated access operation activated by the wordline select pulse is complete. Multiple test rows may be cascaded among columns to provide a long delay line or ring oscillator for improved measurement resolution.

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