Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2005-12-28
2008-10-07
Chaudhari, Chandra (Department: 2891)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C257SE21637
Reexamination Certificate
active
07432147
ABSTRACT:
A method of manufacturing a semiconductor device comprises: forming a device isolation, a first conductivity type region, and a second conductivity type region on a semiconductor substrate; depositing a gate insulating film on an entire surface of the semiconductor substrate; forming a first metal film on the gate insulating film; forming a region of a second metal film so as to cover a region that forms a gate electrode of the first conductivity type region; removing the first metal film exposed outside the region of the second metal film by wet etching to expose the gate insulating film; forming a third metal film on the entire surface of the semiconductor substrate; depositing a protecting film on the third metal film; and patterning the first metal film, the second metal film, the third metal film, and the protecting film to form the gate electrode.
REFERENCES:
patent: 6483151 (2002-11-01), Wakabayashi et al.
patent: 6492217 (2002-12-01), Bai et al.
patent: 6727130 (2004-04-01), Kim et al.
patent: 7-221193 (1995-08-01), None
patent: 2002-289700 (2002-10-01), None
patent: 2003-045995 (2003-02-01), None
Samavedam et al., “Dual-Metal Gate CMOS with HfO2Gate Dielectric”, IEEE, IEDM Technical Digest, pp. 433-436, (2002).
Notification of Reason(s) for Refusal issued by the Japanese Patent Office on May 30, 2008, for Japanese Patent Application No. 2004-381251, and English-language translation thereof.
Chaudhari Chandra
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Kabushiki Kaisha Toshiba
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