Memory address generating apparatus, processor having the...

Details Memory address generating apparatus, processor having the... Memory address generating apparatus, processor having the...

2006-04-10

2008-08-05

Ton, David (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Data formatting to improve error detection correction...

C711S202000

Reexamination Certificate

active

07409607

ABSTRACT:
A memory address generating apparatus comprising an address converting circuit, after setting a first setting region storing substitution source data and a second setting region storing substitution destination data that are a substitution target of the substitution source data in an address space provided by the memory, if a specified address specified by the processor as the access destination to the memory is included between a first beginning address and an end address of the first setting region, changing the specified address to a substitution destination address generated by adding a difference between the specified address and the first beginning address to a second beginning address of the second setting region.

REFERENCES:
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patent: 6260082 (2001-07-01), Barry et al.
patent: 6681346 (2004-01-01), James et al.
patent: 7188231 (2007-03-01), Vavro
patent: 2006/0047937 (2006-03-01), Selvaggi et al.
patent: 6-337812 (1994-06-01), None

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