Trilayer resist scheme for gate etching applications

Details Trilayer resist scheme for gate etching applications Trilayer resist scheme for gate etching applications

2006-08-18

2008-10-14

Picardat, Kevin M (Department: 2822)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

C438S163000, C438S585000

Reexamination Certificate

active

07435671

ABSTRACT:
A trilayer resist (TLR) patterning scheme is provided to enable gate conductors, particularly polySi gate conductors, with critical dimensions (CDs) of less than 40 nm and minimal LER and LWR. In accordance with the present invention, the inventive patterning scheme utilizes an organic/inorganic/organic multilayer stack instead of an organic layer used in the prior art. The top organic layer of the inventive TLR is a photoresist material such as a 193 nm photoresist that is located atop an antireflective coating (ARC), which is also comprised of an organic material. The middle inorganic layer of the TLR comprises any oxide layer such as, for example, a low temperature (less than or equal to 250° C.) chemical vapor deposited (CVD) oxide, an oxide derived from TEOS (tetraethylorthosilicate), silicon oxide, a silane oxide, or a Si-containing ARC material. The bottom organic layer of the TLR comprises any organic layer such as, for example, a Near Frictionless Carbon (NFC), a diamond-like carbon, a thermosetting polyarylene ether.

REFERENCES:
patent: 6605514 (2003-08-01), Tabery et al.
patent: 7301206 (2007-11-01), Yeo et al.
patent: 2006/0094230 (2006-05-01), Fuller et al.
patent: 2007/0045230 (2007-03-01), Keller et al.

Affiliated with

Also associated with

Rating

Trilayer resist scheme for gate etching applications does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Trilayer resist scheme for gate etching applications, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Trilayer resist scheme for gate etching applications will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3990501