Method and system for an on-chip AC self-test controller

Details Method and system for an on-chip AC self-test controller Method and system for an on-chip AC self-test controller

2005-12-30

2008-09-30

Kerveros, James C (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

Reexamination Certificate

active

07430698

ABSTRACT:
A method and system for performing AC self-test on an integrated circuit that includes a system clock for use during normal operation are provided. The method includes applying a long data capture pulse to a first test register in response to the system clock, applying an at speed data launch pulse to the first test register in response to the system clock, inputting the data from the first register to a logic path in response to applying the at speed data launch pulse to the first test register, applying an at speed data capture pulse to a second test register in response to the system clock, inputting the logic path output to the second test register in response to applying the at speed data capture pulse to the second test register, and applying a long data launch pulse to the second test register in response to the system clock.

REFERENCES:
patent: 4916388 (1990-04-01), Sano
patent: 5329532 (1994-07-01), Ikeda et al.
patent: 5444715 (1995-08-01), Gruetzner et al.
patent: 6021514 (2000-02-01), Koprowski
patent: 6178534 (2001-01-01), Day et al.
patent: 6219811 (2001-04-01), Gruetzner et al.
patent: 6510534 (2003-01-01), Nadeau-Dostie et al.
patent: 6629276 (2003-09-01), Hoffman et al.
Research Disclosure (409143); Title: “Built-In Self Test Circuit with PLL (Phase-Locked Loop) Circuit”; p. 653; May 1998.
Research Disclosure (410108); Title: “SRAM Cycle Time Test Procedure”; p. 790; Jun. 1998; Disclosed by: International Business Machines Corporation.
Research Disclosure, Dec. 1992, No. 344; Title: “AC Self-Test Across Asynchronous Logic Partitions”; AT887-0811 TET; Authors: J.R. Dillinger, J.R. Ripley and J.S. Thornley; Published by Kenneth Mason Publications Ltd, England.
Research Disclosure 430181, Feb. 2000, p. 394; Title: “Scanning using on-product clock generation”; Disclosed by International Business Machines Corporation.
IBM Technical Disclosure Bulletin, vol. 33, No. 1B, Jun. 1990; AT887-1042 TET; Authors: H.B. Bakoglu, T.K. Jaber, I. M. Ratiu, K. Shah and W. G. Tuten; Title: “Built-In Self-Test of Arrays Embedded in Logic Chips”; pp. 306-309.
IBM Technical Disclosure Bulletin, vol. 35, No. 1B, Jun. 1992; AT891-0639 CKS; Author: T. Jaber; Title: “AC Array Self-Test”; pp. 73-76.

Affiliated with

Also associated with

Rating

Method and system for an on-chip AC self-test controller does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and system for an on-chip AC self-test controller, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and system for an on-chip AC self-test controller will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3983603