Targets for measurements in semiconductor devices

Details Targets for measurements in semiconductor devices Targets for measurements in semiconductor devices

2005-04-29

2008-09-23

Louie, Wai-Sing (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Test or calibration structure

C257SE21521

Reexamination Certificate

active

07427774

ABSTRACT:
Targets or test structures used for measurements in semiconductor devices having long lines exceeding design rule limitations are divided into segments. In one embodiment, the segments have periodicity in a direction parallel to the length of the lines. In another embodiment, the segments of test structures in adjacent lines do not have periodicity in a direction parallel to the length of the lines. The lack of periodicity is achieved by staggering segments of substantially equal lengths in adjacent lines, or by dividing the lines into segments having unequal lengths. The test structures may be formed in scribe line regions or die regions of a semiconductor wafer.

REFERENCES:
patent: 6822260 (2004-11-01), Nariman et al.
patent: 2005/0089775 (2005-04-01), Archie et al.
Niu, X., “Specular Spectroscopic Scatterometry in DUV Lithography,” Metrology, Inspection, and Process Control for Microlithography XIII, 1999, pp. 159-168, SPIE Proceedings, vol. 3677, Paper No. 3677-18, SPIE—The International Society for Optical Engineering, Bellingham, WA.

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