Top layers of metal for high performance IC's

Details Top layers of metal for high performance IC's Top layers of metal for high performance IC's

2007-10-31

2008-09-23

Louie, Wai-Sing (Department: 2814)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S623000, C438S624000, C438S637000, C257SE21597

Reexamination Certificate

active

07427560

ABSTRACT:
A barrier layer is deposited over a layer of passivation including in an opening to a contact pad created in the layer of passivation. A column of three layers of metal is formed overlying the barrier layer and aligned with the contact pad and having a diameter that is about equal to the surface of the contact pad. The three metal layers of the column comprise, in succession when proceeding from the layer that is in contact with the barrier layer, a layer of pillar metal, a layer of under bump metal and a layer of solder metal. The layer of pillar metal is reduced in diameter, the barrier layer is selectively removed from the surface of the layer of passivation after which reflowing of the solder metal completes the solder bump of the invention.

REFERENCES:
patent: 6087250 (2000-07-01), Hyakutake
patent: 6121159 (2000-09-01), Pasch
patent: 6174810 (2001-01-01), Islam et al.

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