Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2005-07-25
2008-01-01
Smith, Matthew (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S197000, C438S589000, C257SE21679, C257SE21422, C257SE21646, C257SE27103, C257SE29304
Reexamination Certificate
active
07314798
ABSTRACT:
A method of making an array of storage cells includes a first source/drain region underlying a first trench defined in a semiconductor substrate and a second source/drain region underlying a second trench in the substrate. A charge storage stack lines each of the trenches where the charge storage stack includes a layer of discontinuous storage elements (DSEs). A control gate overlies the first trench. The control gate may run perpendicular to the trenches and traverse the first and second trenches. In another implementation, the control gate runs parallel with the trenches. The storage cell may include one or more diffusion regions occupying an upper surface of the substrate between the first and second trenches. The diffusion region may reside between first and second control gates that are parallel to the trenches. Alternatively, a pair of diffusion regions may occur on either side of a control gate that is perpendicular to the trenches.
REFERENCES:
patent: 4184207 (1980-01-01), McElroy
patent: 4751558 (1988-06-01), Kenney
patent: 4785337 (1988-11-01), Kenney
patent: 4833094 (1989-05-01), Kenney
patent: 4860070 (1989-08-01), Arimoto et al.
patent: 5196722 (1993-03-01), Bergendahl et al.
patent: 5252845 (1993-10-01), Kim et al.
patent: 5315142 (1994-05-01), Acovic et al.
patent: 5432365 (1995-07-01), Chin et al.
patent: 5567635 (1996-10-01), Acovic et al.
patent: 5705415 (1998-01-01), Orlowski et al.
patent: 5721448 (1998-02-01), Hauf et al.
patent: 5824580 (1998-10-01), Hauf et al.
patent: 5914523 (1999-06-01), Bashir et al.
patent: 5923046 (1999-07-01), Tezuka et al.
patent: 5969383 (1999-10-01), Chang et al.
patent: 5998263 (1999-12-01), Sekariapuram et al.
patent: 6074954 (2000-06-01), Lill et al.
patent: 6117733 (2000-09-01), Sung et al.
patent: 6121148 (2000-09-01), Bashir et al.
patent: 6228706 (2001-05-01), Horak et al.
patent: 6265268 (2001-07-01), Halliyal et al.
patent: 6281064 (2001-08-01), Mandelman et al.
patent: 6307782 (2001-10-01), Sadd et al.
patent: 6320784 (2001-11-01), Muralidhar et al.
patent: 6330184 (2001-12-01), White et al.
patent: 6365452 (2002-04-01), Perng et al.
patent: 6399441 (2002-06-01), Ogura et al.
patent: 6486028 (2002-11-01), Chang et al.
patent: 6559032 (2003-05-01), Gonzalez et al.
patent: 6583466 (2003-06-01), Lin et al.
patent: 6638810 (2003-10-01), Bakli et al.
patent: 6673681 (2004-01-01), Kocon et al.
patent: 6674120 (2004-01-01), Fujiwara
patent: 6677204 (2004-01-01), Cleeves et al.
patent: 6706599 (2004-03-01), Sadd et al.
patent: 6750499 (2004-06-01), Wu
patent: 6803620 (2004-10-01), Moriya et al.
patent: 6818512 (2004-11-01), Hsieh
patent: 6818939 (2004-11-01), Hadizad
patent: 6894339 (2005-05-01), Fan et al.
patent: 6916715 (2005-07-01), Hsiao et al.
patent: 6936887 (2005-08-01), Harari et al.
patent: 7015537 (2006-03-01), Lee et al.
patent: 7078286 (2006-07-01), Mehta
patent: 7098502 (2006-08-01), Mathew et al.
patent: 7199419 (2007-04-01), Haller
patent: 7211858 (2007-05-01), Prinz
patent: 7220634 (2007-05-01), Prall et al.
patent: 2002/0151136 (2002-10-01), Lin et al.
patent: 2003/0062565 (2003-04-01), Yamazaki et al.
patent: 2003/0068864 (2003-04-01), Il-yong et al.
patent: 2004/0000688 (2004-01-01), Harari et al.
patent: 2004/0121540 (2004-06-01), Lin
patent: 2004/0248371 (2004-12-01), Wang
patent: 2005/0037576 (2005-02-01), Chen et al.
patent: 2005/0148173 (2005-07-01), Shone
patent: 2005/0259475 (2005-11-01), Forbes
patent: 2005/0280089 (2005-12-01), Forbes
patent: 2005/0280094 (2005-12-01), Forbes
patent: 2006/0011966 (2006-01-01), Wang
patent: 2006/0046383 (2006-03-01), Chen et al.
patent: 2006/0131640 (2006-06-01), Yu et al.
patent: 2006/0152978 (2006-07-01), Forbes
patent: 2006/0166443 (2006-07-01), Forbes
Osabe, et al. “Charge-Injection Length in Silicon Nanocrystal Memory Cells,” VLSI, p. 242, 2004.
Ma, et al. “A Dual-Bit Split-Gate EEPROM (DSG) Cell in Contactless Array for Single-Vcc High Density Flash Memories,” IEDM, p. 57-60, 1994.
“Twin MONOS Cell with Dual Control Gates,” VLSI Technology, Source-Side Injection Cell with Two Storage Regions Forming in Nitride, p. 122, 2000.
“Vertical Floating-Gate 4.5/sup 2/split-gate NOR Flash Memory at 110nm Node,” VLSI Technology, Source-Side Injection Cell in a Trench, p. 72, 2004.
U.S. Appl. No. 10/961,295, filed Oct. 8, 2004.
U.S. Appl. No. 11/188,582, filed Jul. 25, 2005.
U.S. Appl. No. 11/188,584, filed Jul. 25, 2005.
U.S. Appl. No. 11/188,585, filed Jul. 25, 2005.
U.S. Appl. No. 11/188,588, filed Jul. 25, 2005.
U.S. Appl. No. 11/188,591, filed Jul. 25, 2005.
U.S. Appl. No. 11/188,603, filed Jul. 25, 2005.
U.S. Appl. No. 11/188,604, filed Jul. 25, 2005.
U.S. Appl. No. 11/188,615, filed Jul. 25, 2005.
U.S. Appl. No. 11/188,898, filed Jul. 25, 2005.
U.S. Appl. No. 11/188,909, filed Jul. 25, 2005.
U.S. Appl. No. 11/188,910, filed Jul. 25, 2005.
U.S. Appl. No. 11/188,935, filed Jul. 25, 2005.
U.S. Appl. No. 11/188,939, filed Jul. 25, 2005.
U.S. Appl. No. 11/188,953, filed Jul. 25, 2005.
U.S. Appl. No. 11/188,999, filed Jul. 25, 2005.
U.S. Appl. No. 11/525,747, filed Sep. 22, 2006.
Guan, H., et al. “An Analytical Model for Optimization of Programming Efficiency and Uniformity of Split Gate Source-Side Injection Superflash Memory,” IEEE Transactions on Electron Devices, vol. 50, No. 3, pp. 809-815, Mar. 2003.
Hayashi, Y., et al. “Twin MONOS Cell with Dual Control Gates,” 2000 Symposium on VLSI Technology Digest of Technical Papers, pp. 122-123, 2000.
Lee, D., et al. “Vertical Floating-Gate 4.5F2 Split-Gate NOR Flash Memory at 110nm Node,” 2004 Symposium on VLSI Technology Digest of Technical Papers, pp. 72-73, 2004.
Van Houdt, J., et al. “An Analytical Model for the Optimization of Source-Side Injection Flash EEPROM Devices,” IEEE Transactions on Electron Devices, vol. 42, No. 7, pp. 1314-1320, Jul. 1995.
Actions on the Merits by U.S.P.T.O, as of Jul. 26, 2007, 8 pages.
U.S. Appl. No. 11/626,762, filed Jan. 24, 2007.
U.S. Appl. No. 11/626,753, filed Jan. 24, 2007.
U.S. Appl. No. 11/626,768, filed Jan. 24, 2007.
Chindalore Gowrishankar L.
Hong Cheong M.
Swift Craig T.
Freescale Semiconductor Inc.
Smith Matthew
Stark Jarrett J
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