MOS transistor with elevated source/drain structure

Details MOS transistor with elevated source/drain structure MOS transistor with elevated source/drain structure

2008-05-06

2008-05-06

Huynh, Andy (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S336000, C257SE21430, C257SE21431, C438S300000

Reexamination Certificate

active

11388868

ABSTRACT:
In a metal-oxide semiconductor (MOS) transistor with an elevated source/drain structure and in a method of fabricating the MOS transistor with the elevated source/drain structure using a selective epitaxy growth (SEG) process, a source/drain extension junction is formed after an epi-layer is formed, thereby preventing degradation of the source/drain junction region. In addition, the source/drain extension junction is partially overlapped by a lower portion of the gate layer, since two gate spacers are formed and two elevated source/drain layers are formed in accordance with the SEG process. This mitigates the short channel effect and reduces sheet resistance in the source/drain layers and the gate layer.

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Notice of Office Action issued on Nov. 16, 2007 for Chinese Application No. 2004/100433165 (with English-language translation).

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