Semiconductor fabrication process for integrating formation...

Details Semiconductor fabrication process for integrating formation... Semiconductor fabrication process for integrating formation...

Filed on

2008-04-29

Date issued

2008-04-29

Examiner

Chaudhari, Chandra (Department: 2891)

Patent Class

Semiconductor device manufacturing: process

SubClass

Making field effect device having pair of active regions...

SubSubClass

Having insulated gate

Other Related Categories

C438S962000, C257SE21689

Type

Reexamination Certificate

Status

active

Patent number

11172728

Description

ABSTRACT:
A semiconductor fabrication process includes forming polysilicon nanocrystals on a tunnel oxide overlying a first region of a substrate. A second dielectric is deposited overlying the first region and a second region. Without providing any protective layer overlying the second dielectric in the first region, an additional thermal oxidation step is performed without oxidizing the nanocrystals. A gate electrode film is then deposited over the second dielectric and patterned to form first and second gate electrodes. The second dielectric may be an annealed, CVD oxide. The additional thermal oxidation may include forming by dry oxidation a third dielectric overlying a third region of the semiconductor substrate. The dry oxidation produces a interfacial silicon oxide underlying the second dielectric in the second region. An upper surface of a fourth region of the substrate may then be exposed and a fourth dielectric formed on the upper surface in the fourth region.

REFERENCES:
patent: 6060743 (2000-05-01), Sugiyama et al.
patent: 6297095 (2001-10-01), Muralidhar et al.
patent: 6531731 (2003-03-01), Jones et al.

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