Post passivation method for semiconductor chip or wafer

Details Post passivation method for semiconductor chip or wafer Post passivation method for semiconductor chip or wafer

2008-07-29

2008-07-29

Ha, Nathan W (Department: 2814)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

Reexamination Certificate

active

10154662

ABSTRACT:
The present invention adds one or more thick layers of polymer dielectric and one or more layers of thick, wide metal lines on top of a finished semiconductor wafer, post-passivation. The thick, wide metal lines may be used for long signal paths and can also be used for power buses or power planes, clock distribution networks, critical signal, and re-distribution of I/O pads for flip chip applications. Photoresist defined electroplating, sputter/etch, or dual and triple damascene techniques are used for forming the metal lines and via fill.

REFERENCES:
patent: 4188636 (1980-02-01), Sato et al.
patent: 4423547 (1984-01-01), Farrar et al.
patent: 4618878 (1986-10-01), Aoyama et al.
patent: 4980034 (1990-12-01), Volfson et al.
patent: 5055907 (1991-10-01), Jacobs
patent: 5083187 (1992-01-01), Lamson et al.
patent: 5106461 (1992-04-01), Volfson et al.
patent: 5212403 (1993-05-01), Nakanishi et al.
patent: 5262353 (1993-11-01), Sun et al.
patent: 5360524 (1994-11-01), Hendel et al.
patent: 5384488 (1995-01-01), Golshan et al.
patent: 5468984 (1995-11-01), Efland et al.
patent: 5501006 (1996-03-01), Gehman, Jr. et al.
patent: 5563086 (1996-10-01), Bertin et al.
patent: 5635767 (1997-06-01), Wenzel et al.
patent: 5659201 (1997-08-01), Wollesen
patent: 5665639 (1997-09-01), Seppala et al.
patent: 5686764 (1997-11-01), Fulcher
patent: 5719448 (1998-02-01), Ichikawa
patent: 5726499 (1998-03-01), Irinoda
patent: 5789303 (1998-08-01), Leung et al.
patent: 5818110 (1998-10-01), Cronin
patent: 5827776 (1998-10-01), Bandyopadhyay et al.
patent: 5827778 (1998-10-01), Yamada
patent: 5834844 (1998-11-01), Akagawa et al.
patent: 5861675 (1999-01-01), Sasaki et al.
patent: 5910020 (1999-06-01), Yamada
patent: 5939790 (1999-08-01), Gregoire et al.
patent: 5953626 (1999-09-01), Hause et al.
patent: 5965903 (1999-10-01), Chittipeddi et al.
patent: 5969424 (1999-10-01), Matsuki et al.
patent: 6016000 (2000-01-01), Moslehi
patent: 6020640 (2000-02-01), Efland et al.
patent: 6025275 (2000-02-01), Efland et al.
patent: 6025639 (2000-02-01), Mitwalsky et al.
patent: 6087250 (2000-07-01), Hyakutake
patent: 6100548 (2000-08-01), Nguyen et al.
patent: 6103552 (2000-08-01), Lin
patent: 6124198 (2000-09-01), Moslehi
patent: 6130457 (2000-10-01), Yu et al.
patent: 6130481 (2000-10-01), Harada et al.
patent: 6144100 (2000-11-01), Shen et al.
patent: 6184138 (2001-02-01), Ho et al.
patent: 6184143 (2001-02-01), Ohashi et al.
patent: 6187680 (2001-02-01), Costrini et al.
patent: 6207486 (2001-03-01), Nishiyama
patent: 6218223 (2001-04-01), Ikeda et al.
patent: 6218318 (2001-04-01), Ohkura et al.
patent: 6229221 (2001-05-01), Kloen et al.
patent: 6242336 (2001-06-01), Ueda et al.
patent: 6272736 (2001-08-01), Lee
patent: 6294451 (2001-09-01), Yoshizawa
patent: 6303423 (2001-10-01), Lin
patent: 6303977 (2001-10-01), Schroen et al.
patent: 6346471 (2002-02-01), Okushima
patent: 6348733 (2002-02-01), Lin
patent: 6350705 (2002-02-01), Lin
patent: 6359328 (2002-03-01), Dubin
patent: 6370768 (2002-04-01), Itabashi
patent: 6376374 (2002-04-01), Stevens
patent: 6383916 (2002-05-01), Lin
patent: 6392300 (2002-05-01), Koike
patent: 6436814 (2002-08-01), Horak et al.
patent: 6455885 (2002-09-01), Lin
patent: 6459135 (2002-10-01), Basteres et al.
patent: 6472745 (2002-10-01), Iizuka
patent: 6489647 (2002-12-01), Lin
patent: 6495442 (2002-12-01), Lin et al.
patent: 6518092 (2003-02-01), Kikuchi
patent: 6544880 (2003-04-01), Akram
patent: 6555459 (2003-04-01), Tokushige et al.
patent: 6583043 (2003-06-01), Shroff et al.
patent: 6593649 (2003-07-01), Lin et al.
patent: 6614091 (2003-09-01), Downey et al.
patent: 6620728 (2003-09-01), Lin
patent: 6649509 (2003-11-01), Lin et al.
patent: 6673704 (2004-01-01), Wada et al.
patent: 6707159 (2004-03-01), Kumamoto et al.
patent: 6710460 (2004-03-01), Morozumi
patent: 6720212 (2004-04-01), Robl et al.
patent: 6756295 (2004-06-01), Lin et al.
patent: 6762115 (2004-07-01), Lin et al.
patent: 6798073 (2004-09-01), Lin et al.
patent: 6800555 (2004-10-01), Test et al.
patent: 6818546 (2004-11-01), Saito et al.
patent: 6838769 (2005-01-01), Chittipeddi et al.
patent: 6864562 (2005-03-01), Toyosawa et al.
patent: 7091616 (2006-08-01), Suminoe et al.
patent: 2002/0017730 (2002-02-01), Tahara et al.
patent: 2002/0024142 (2002-02-01), Sekiguchi
patent: 2002/0158334 (2002-10-01), Vu et al.
patent: 01-135043 (1989-05-01), None
patent: 01-183836 (1989-07-01), None
patent: 01-184848 (1989-07-01), None
patent: 01-184849 (1989-07-01), None
patent: 04-316351 (1992-11-01), None
Stanley Wolf, Ph.D.,Silicon Processing for the VLSI Era: vol. 2 Process Integration, Lattice Press, Sunset Beach, CA, USA Copyright 1990, pp. 214-217, 282-285.

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