Semiconductor device with high-k gate dielectric and...

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C257S371000, C257S410000, C257SE27046

Reexamination Certificate

active

11185443

ABSTRACT:
A process and apparatus for a semiconductor device is provided. A device comprises a first transistor having a first charge carrier type. The first transistor comprises a high-k gate dielectric and a first doped electrode. The first charge carrier type comprises one of p-type and n-type and the first doped electrode comprises the other of p-type and n-type. The device further comprises a second transistor having a charge carrier type opposite the first charge carrier type. The second transistor comprises the high-k gate dielectric, and a second doped electrode, wherein the second doped electrode comprises the other of p-type and n-type.

REFERENCES:
patent: 6063698 (2000-05-01), Huang et al.
patent: 6136654 (2000-10-01), Kraft et al.
patent: 6174755 (2001-01-01), Liaw
patent: 6174775 (2001-01-01), Liaw
patent: 6232163 (2001-05-01), Voldman et al.
patent: 6255698 (2001-07-01), Gardner et al.
patent: 6297103 (2001-10-01), Ahn et al.
patent: 6352885 (2002-03-01), Wieczorek et al.
patent: 6359311 (2002-03-01), Colinge et al.
patent: 6479403 (2002-11-01), Tsei et al.
patent: 6566205 (2003-05-01), Yu et al.
patent: 6596599 (2003-07-01), Guo
patent: 6614067 (2003-09-01), Liaw
patent: 6632714 (2003-10-01), Yoshikawa
patent: 6706581 (2004-03-01), Hou et al.
patent: 6716695 (2004-04-01), Hattangady et al.
patent: 6720221 (2004-04-01), Ahn et al.
patent: 6743704 (2004-06-01), Takahashi
patent: 6746900 (2004-06-01), Lin et al.
patent: 2002/0168826 (2002-11-01), Jin et al.
patent: 2003/0042548 (2003-03-01), Maeda et al.
patent: 2003/0211880 (2003-11-01), Arghavani et al.
patent: 2004/0026687 (2004-02-01), Grupp et al.
patent: 2004/0033676 (2004-02-01), Arghavani et al.
patent: 2004/0082125 (2004-04-01), Hou et al.
patent: 2004/0087075 (2004-05-01), Wang et al.
patent: 2004/0106287 (2004-06-01), Chau et al.
patent: 2004/0110361 (2004-06-01), Parker et al.
patent: 2004/0121541 (2004-06-01), Doczy et al.
patent: 2004/0124476 (2004-07-01), Miyano
patent: 2004/0142524 (2004-07-01), Grupp et al.
patent: 2004/0164318 (2004-08-01), Lee et al.
patent: 2005/0136584 (2005-06-01), Boyanov et al.
patent: 2005/0269650 (2005-12-01), Pidin
Diaz, C. H., “Bulk CMOS Technology for SOC,” Extended Abstracts of International Workshop in Junction Technology, Japan Society of Applied Physics, 2002, pp. 91-96.
Fung, S. K. H., et al., “65nm CMOS High Speed, General Purpose and Low Power Transistor Technology for High Volume Foundry Application,” Symposium on VLSI Technology Digest of Technical Papers, IEEE, 2004, pp. 92-93.
Hu, C., “Device Challenges and Opportunities,” Symposium on VLSI Technology Digest of Technical Papers, IEEE, 2004, pp. 4-5.
Iwamoto, T., et al., “A Highly Manufacturable Low Power and High Speed HfSiO CMOS FET with Dual Poly-Si Gate Electrodes,” IEEE, 2003, 4 pages.
Shi, Z., et al., “Mobility Enhancement in Surface Channel SiGe PMOSFETs with HfO2Gate Dielectrics,” Electron Device Letters, IEEE, Jan. 2003, pp. 34-36, vol. 24, No. 1.
Shima, M., “<100> Strained-SiGe-Channel p-MOSFET with Enhanced Hole Mobility and Lower Parasitic Resistance,” FUJITSU Sci. Tech. J., Jun. 2003, pp. 78-83, vol. 39, No. 1.
Shiraishi, K., et al., “Physics in Fermi Level Pinning at the PolySi/Hf-based High-k Oxide Interface,” Symposium on VLSI Technology Digest of Technical Papers, IEEE, 2004, pp. 108-109.
Weber, O., et al., “55nm High Mobility SiGe(:C) pMOSFETs with HfO2Gate Dielectric and TiN Metal Gate for Advanced CMOS,” Symposium on VLSI Technology Digest of Technical Papers, 2004, pp. 42-43.
Yang, C. W., et al., “Effect of Polycrystalline-silicon Gate Types on the Opposite Flatband Voltage Shift inn-type andp-type Metal-oxide-semiconductor Field-effect Transistors for High-k-HfO2Dielectric,” Applied Physics Letters, American Institute of Physics, Jul. 14, 2003, pp. 308-310, vol. 83, No. 2.
Sekine, K., et al., “Nitrogen Profile Control by Plasma Nitridation Technique for Poly-Si Gate HfSiON CMOSFET with Excellent Interface Property and Ultra-low Leakage Current,” IEEE, 2003, pp. 103-106.
Wang, C.-H., et al., “Low Power Device Technology with SiGe channnel, HfSiON, and poly-Si Gate,” pp. 1-3.
Tamura, Y., et al., “SiN-capped HfSiON Gate Stacks with Improved Bias Temperature Instabilities for 65 nm-node Low-Standby-Power Transistors,” 2004 Symposium on VLSI Technology Digest of Technical Papers, IEEE, 2004, pp. 210-211.
Ma, T. P., “Making Silicon Nitride Film a Viable Gate Dielectric,” IEEE Transactions of Electron Devices, vol. 45, No. 3, Mar. 1998, pp. 680-690.
Cartier, E., et al., “Systematic study of pFET Vtwith Hf-based gate stacks with poly-SI and FUSI gates,” 2004 Symposium on VLSI Technology, Digest of Technical Papers, pp. 44-45.
Fernandez, F.A., et al., “Properties of Si3N4/SixGe1−xMetal-Insulator-Semiconductor Capacitors,” Electronics Letters, Sep. 26, 1991, vol. 27, No. 20, pp. 1826-1827.
Yeo, Y-C., et al., “Enhanced Performance in Sub-100 nm CMOSFETs using Strained Epitaxial Silicon-Geranium,” IEDM 2000, pp. 753-756.
Lu, W., et al., “p-Type SiGe Transistors with Low Gate Leakage Using SiN Gate Dielectric,” IEEE Electron Device Letters, vol. 20, No. 10, Oct. 1999, pp. 514-516.
She, M., et al., “JVD Silicon Nitride as Tunnel Dielectric in p-Channel Flash Memory,” IEEE Electron Device Letters, vol. 23, No. 2, Feb. 2002, pp. 91-93.
Khare, M., et al., “Highly Robust Ultra-Thin Dielectric for Giga Scale Technology,” 1998 Symposium on VLSI Technology Digest of Technical Papers, pp. 218-219.
Wang, D. et al., “High-Quality MNS Capacitors Prepared by Jet Vapor Deposition at Room Temperature,” IEEE Electron Device Letters, vol. 13, No. 9, Sep. 1992, pp. 482-484.
Tseng, H.-H., et al., “Ultra-Thin Decoupled Plasma Nitridation (DPN) Oxynitride Gate Dielectric for 80-nm Advanced Technology,” IEEE Electron Device Letters, vol. 23, No. 12, Dec. 2002, pp. 704-706.
Tseng, H.-H., et al., “Threshold Voltage Instability and Plasma Induced Damage of PolySi/HfO2 Devices—Positive Impact of Deuterium Incorporation,” 2004 IEEE International Conference on Integrated Circuit Design and Technology, pp. 255-259.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Semiconductor device with high-k gate dielectric and... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor device with high-k gate dielectric and..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device with high-k gate dielectric and... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3903062

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.