Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2007-11-27
2007-11-27
Weiss, Howard (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
Reexamination Certificate
active
10700869
ABSTRACT:
A static memory element includes a first inverter having an input coupled to a left bit node and an output coupled to a right bit node. A second inverter has an input coupled to the right bit node and an output coupled to the left right bit node. A first fully depleted semiconductor-on-insulator transistor has a drain coupled to the left bit node, and a second fully depleted semiconductor-on-insulator transistor has a drain coupled to the right bit node.
REFERENCES:
patent: 4314269 (1982-02-01), Fujiki
patent: 4631803 (1986-12-01), Hunter et al.
patent: 4946799 (1990-08-01), Blake et al.
patent: 5447884 (1995-09-01), Fahey et al.
patent: 5461250 (1995-10-01), Burghartz et al.
patent: 5534713 (1996-07-01), Ismail et al.
patent: 5607865 (1997-03-01), Choi et al.
patent: 5629544 (1997-05-01), Voldman et al.
patent: 5714777 (1998-02-01), Ismail et al.
patent: 5763315 (1998-06-01), Benedict et al.
patent: 5770881 (1998-06-01), Pelella et al.
patent: 5811857 (1998-09-01), Assaderaghi et al.
patent: 6008095 (1999-12-01), Gardner et al.
patent: 6015993 (2000-01-01), Voldman et al.
patent: 6040991 (2000-03-01), Ellis-Monaghan et al.
patent: 6046487 (2000-04-01), Benedict et al.
patent: 6059895 (2000-05-01), Chu et al.
patent: 6061267 (2000-05-01), Houston
patent: 6198173 (2001-03-01), Huang
patent: 6222234 (2001-04-01), Imai
patent: 6232163 (2001-05-01), Voldman et al.
patent: 6258664 (2001-07-01), Reinberg
patent: 6291321 (2001-09-01), Fitzgerald
patent: 6294834 (2001-09-01), Yeh et al.
patent: 6341083 (2002-01-01), Wong
patent: 6342410 (2002-01-01), Yu
patent: 6358791 (2002-03-01), Hsu et al.
patent: 6387739 (2002-05-01), Smith, III
patent: 6413802 (2002-07-01), Hu et al.
patent: 6414355 (2002-07-01), An et al.
patent: 6429061 (2002-08-01), Rim
patent: 6448114 (2002-09-01), An et al.
patent: 6475838 (2002-11-01), Bryant et al.
patent: 6475869 (2002-11-01), Yu
patent: 6489664 (2002-12-01), Re et al.
patent: 6524905 (2003-02-01), Yamamichi et al.
patent: 6525403 (2003-02-01), Inaba et al.
patent: 6549450 (2003-04-01), Hsu et al.
patent: 6555839 (2003-04-01), Fitzgerald
patent: 6558998 (2003-05-01), Belleville et al.
patent: 6605514 (2003-08-01), Tabery et al.
patent: 6611029 (2003-08-01), Ahmed et al.
patent: 6621131 (2003-09-01), Murthy et al.
patent: 6635909 (2003-10-01), Clark et al.
patent: 6642090 (2003-11-01), Fried et al.
patent: 6653700 (2003-11-01), Chau et al.
patent: 6720619 (2004-04-01), Chen et al.
patent: 6762448 (2004-07-01), Lin et al.
patent: 6855990 (2005-02-01), Yeo et al.
patent: 6867433 (2005-03-01), Yeo et al.
patent: 2002/0076899 (2002-06-01), Skotnicki et al.
patent: 2002/0153549 (2002-10-01), Laibowitz et al.
patent: 2002/0190284 (2002-12-01), Murth et al.
patent: 2003/0001219 (2003-01-01), Chau et al.
patent: 2003/0030091 (2003-02-01), Bulsara et al.
patent: 2003/0080386 (2003-05-01), Ker et al.
patent: 2004/0007715 (2004-01-01), Webb et al.
patent: 2004/0026765 (2004-02-01), Currie et al.
patent: 2004/0031979 (2004-02-01), Locktefeld et al.
patent: 2004/0061178 (2004-04-01), Lin et al.
patent: 2004/0075122 (2004-04-01), Lin et al.
patent: WO 03/017336 (2003-02-01), None
Yang, F.-L.., et al., “Strained FIP-SOI (FinFET/FD/PD-SOI) for Sub-65 nm CMOS Scaling.” 2003 Symposium on VLSI Technology Digest of Technical Papers (Jun. 2003) pp. 137-138.
Kuang, J.B., et al., “SRAM Bitline Circuits on PD SPOI: Advantages and Concerns,” IEEE Journal of Solid-State Circuits, vol. 32, No. 6 (Jun. 1997) pp. 837-844.
Shimizu, A., et al., “Local Mechanical-Stress Control (LMC): A New Technique for CMOS-Performance Enhancement,” IEDM 2001 (Dec. 2001) pp. 433-436.
Blaauw, D., et al., “Gate Oxide and Subthreshold Leakage Characterization, Analysis and Optimization,” date unknown, 2 pages.
Cavassilas, N., et al., “Capacitance-voltage Characteristica of Metal-Oxide-Strained Semiconductor Si/SiGe Heterostructures,” Nanotech 2002, vol. 1, pp. 600-603.
Celik, M., et al., “A 45mm Gate Length High Performance SOI Transistors for 100nm CMOS Technology Applications,” 2002 Symposium on VLSI Technology, Digest of Technical Papers, pp. 166-167.
Chang, L., et al., “Direct-Tunneling Gate Leakage Current in Double-Gate and Ultrathin Body MOSFETs,” 2002 IEEE, vol. 49, No. 12, pp. 2288-2295, Dec. 2002.
Chang, L., et al., “Reduction of Direct-Tunneling Gate Leakage Current in Double-Gate and Ultra-Thin Body MOSFETs,” 2001 IEEE, Berkeley, CA.
Chau, R., et al., “A 50 mm Depleted-substrate CMOS Transistor (DST),” International Electron Device Meeting 2001, Technical Digest, pp. 621-624.
Chen, W., et al., “Suppression of the SOI Floating-body Effects by Linked-body Device Structure,” 1996 Symposium on VLSI Technology, Digest of Technical Papers, pp. 92-93.
Fung, SK.H., et al., “Gate Length Scaling to 30nm Regime Using Ultra-thin Film PD-SOI Technology,” International Electron Device Meeting 2001, Technical Digest, pp. 629-632.
Gámiz, F., et al., “Electron Transport in Strained Si Inversion Layers Grown on SiGe-on-Insulator Substrates,” Journal of Applied Physics, vol. 92, No. 1, (Jul. 1, 2002), pp. 288-295.
Gámiz, F., et al., “Strained-Si/SiGe-on-Insulator Inversion Layers: The Role of Strained-Si Layer Thickness on Electron Mobility,” Applied Physics Letters, vol. 80, No. 22, (Jun. 3, 2002), pp. 4160-4162.
Geppert, L., “The Amazing Vanishing Transistor Act,” Oct. 2002, IEEE Spectrum, pp. 28-33.
Huang, X., et al. “Sub-50 nm P-Channel FinFET,” IEEE Transactions on Electron Devices, vol. 48, No. 5 (May 2001) pp. 880-886.
Ismail, K., et al., “Electron Transport Properties of Si/SiGe Heterostructures: Measurements and Device Implications,” Applied Physics Letters, vol. 63, No. 5 (Aug. 2, 1993), pp. 660-662.
Jurczak M., et al., “Silicon-on-Nothing (SON) - an Innovative Process for Advanced CMOS,” IEEE Transactions on Electron Devices, vol. 47, No. 11, (Nov. 2000), pp. 2179-2187.
Jurczak M., et al., “SON (Silicon-on-Noting) - A New Device Architecture For The ULSI Era,” Symposium on VLSI Technology Digest of Technical Papers, (1999), pp. 29-30.
Maiti, C.K., et al., “Film Growth and Material Parameters,” Application of Silicon-Germanium Heterostructure, Institute of Physics Publishing, Ch. 2 (2001) pp. 32-42.
Matthews, J.W., et al., “Defects Associated with the Accommodation of Misfit Between Crystals,” J. Vac. Sci. Technol., vol. 12, No. 1, (Jan./Feb. 1975), pp.126-133.
Matthews, J.W., et al., “Defects in Epitaxial Multilayers - I. Misfit Dislocations,” Journal of Crystal Growth, vol. 27, (1974), pp. 118-125.
Matthews, J.W., et al., “Defects in Epitaxial Multilayers - II. Dislocation Pile-Ups, Threading Dislocation, Slip Lines and Cracks” Journal of Crystal Growth, vol. 29, (1975), pp. 273-280.
Matthews, J.W., et al., “Defects in Epitaxial Multilayers - III. Preperation of Almost Perfect Multilayers,” Journal of Crystal Growth, vol. 32, (1976), pp. 265-273.
Mizuno, T., et al. “Novel SOI p-Channel MOSFETs With Higher Strain in Si Channel Using Double SiGe Heterostructures,” IEEE Transactions on Electron Devices, vol. 49, No. 1 (Jan 2002) pp. 7-14.
Nayak, D.K., et al. “Enhancement-Mode Quantum-Well GexSi1-xPMOS,” IEEE Electron Device Letters, vol. 12, No. 4 (Apr. 1991), pp. 154-156.
Ootsuka, F., et al., “A Highly Dense, High-Performance 130nm Node CMOS Technology for Large Scale System-on-a-Chip Application,” International Electron Device Meeting, (2000), pp. 575-578.
Schüppen, A., et al., “Mesa and Planar SiGe-HBTs on MBE-Wafers,” Journal of Materials Science: Materials in Electronics, vol. 6, (1995), pp. 298-305.
Shahidi, G.G., “SOI Technology for the GHz era,” IBM Journal of Research and Development, vol. 46, No. 2/3 (Mar./May 2002), pp. 121-131.
Tezuka, T., et al., “High-performance Strained Si-on-Ins
Hu Chenming
Yang Fu-Liang
Yeo Yee-Chia
Slater & Matsil L.L.P.
Taiwan Semiconductor Manufacturing Company , Ltd.
Trinh (Vikki) Hoa B.
Weiss Howard
LandOfFree
Semiconductor-on-insulator SRAM configured using... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor-on-insulator SRAM configured using..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor-on-insulator SRAM configured using... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3891063