Optimized planarization process for SOG filled vias

Details Optimized planarization process for SOG filled vias Optimized planarization process for SOG filled vias

1997-09-02

1998-08-11

Chaudhuri, Olik

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

438626, 438631, 438699, 438723, 438903, 438763, H01L 214763

Patent

active

057927057

ABSTRACT:
A planarization process, featuring removal of spin on glass, used to fill narrow spaces between metal lines, has been developed. A dual dielectric, of underlying silicon oxide, and overlying silicon nitride, are initially used to passivate the metal lines, followed by the spin on glass fill. A RIE etchback of the spin on glass proceeds to a point in which the silicon nitride, on the metal line, is exposed. The exposed silicon nitride is then removed leaving a silicon oxide passivated metal line, and seamless insulator filled spaces. The ability of not exposing the passivating silicon oxide to RIE echback process, allows seamless fills to result.

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