Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of... – Insulative material deposited upon semiconductive substrate
Reexamination Certificate
2007-08-07
2007-08-07
Everhart, Caridad (Department: 2891)
Semiconductor device manufacturing: process
Coating of substrate containing semiconductor region or of...
Insulative material deposited upon semiconductive substrate
C257SE21170, C257SE21478
Reexamination Certificate
active
11032859
ABSTRACT:
A method for forming sidewall spacers on a gate stack by depositing one or more layers of silicon containing materials using PECVD process(es) on a gate structure to produce a spacer having an overall k value of about 3.0 to about 5.0. The silicon containing materials may be silicon carbide, oxygen doped silicon carbide, nitrogen doped silicon carbide, carbon doped silicon nitride, nitrogen doped silicon oxycarbide, or combinations thereof. The deposition is performed in a plasma enhanced chemical vapor deposition chamber and the deposition temperature is less than 450° C. The sidewall spacers so produced provide good capacity resistance, as well as excellent structural stability and hermeticity.
REFERENCES:
patent: 6147009 (2000-11-01), Grill et al.
patent: 6169021 (2001-01-01), Akram et al.
patent: 6228758 (2001-05-01), Pellerin et al.
patent: 6251802 (2001-06-01), Moore et al.
patent: 6340435 (2002-01-01), Bjorkman et al.
patent: 6383951 (2002-05-01), Li
patent: 6462371 (2002-10-01), Weimer et al.
patent: 6465366 (2002-10-01), Nemani et al.
patent: 6514671 (2003-02-01), Parikh et al.
patent: 6537733 (2003-03-01), Campana et al.
patent: 6541397 (2003-04-01), Bencher
patent: 6547977 (2003-04-01), Yan et al.
patent: 6573030 (2003-06-01), Fairbairn et al.
patent: 6627532 (2003-09-01), Gaillard et al.
patent: 6656837 (2003-12-01), Xu et al.
patent: 6743732 (2004-06-01), Lin et al.
patent: 6762127 (2004-07-01), Boiteux et al.
patent: 6764958 (2004-07-01), Nemani et al.
patent: 6794311 (2004-09-01), Huang et al.
patent: 6821571 (2004-11-01), Huang
patent: 6893967 (2005-05-01), Wright et al.
patent: 2001/0034121 (2001-10-01), Fu et al.
patent: 2002/0016085 (2002-02-01), Huang et al.
patent: 2002/0054962 (2002-05-01), Huang
patent: 2003/0129827 (2003-07-01), Lee et al.
patent: 2004/0033678 (2004-02-01), Argharvani et al.
patent: 2004/0072446 (2004-04-01), Liu et al.
patent: 2004/0101667 (2004-05-01), O'Loughlin et al.
patent: 2004/0115876 (2004-06-01), Goundar et al.
patent: 2004/0175929 (2004-09-01), Campana et al.
patent: 2004/0192032 (2004-09-01), Ohmori et al.
patent: 2005/0003676 (2005-01-01), Ho et al.
patent: 2005/0026430 (2005-02-01), Kim et al.
patent: 2005/0236694 (2005-10-01), Wu et al.
patent: 2005/0266691 (2005-12-01), Gu et al.
patent: 2005/0287771 (2005-12-01), Seamons et al.
patent: 2006/0033678 (2006-02-01), Lubomirsky et al.
patent: 2006/0102076 (2006-05-01), Smith et al.
patent: 2006/0261490 (2006-11-01), Su et al.
patent: 00/22671 (2000-04-01), None
U.S. Appl. No. 10/828,023, filed Apr. 19, 2004, Rajagopalam et al.
U.S. Appl. No. 11/365,740, filed Feb. 28, 2006, Entitled: Low K Spacer Integration Into CMOS Transistors (APPM/010133).
Arghavani Reza
Kwan Michael Chiu
Xia Li-Qun
Yim Kang Sub
Applied Materials Inc.
Everhart Caridad
Patterson & Sheridan
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