Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2007-02-06
2007-02-06
Fourson, George (Department: 2823)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S365000, C438S233000, C438S672000, C438S595000, C438S303000, C438S283000
Reexamination Certificate
active
10409810
ABSTRACT:
A method for forming a self-aligned contact to an ultra-thin body transistor first providing an ultra-thin body transistor with source and drain regions operated by a gate stack; forming a contact spacer on the gate stack; forming a passivation layer overlying the transistor; forming a contact hole in the passivation layer exposing the contact spacer and the source/drain regions; filling the contact hole with an electrically conductive material; and establishing electrical communication with the source/drain region.
REFERENCES:
patent: 5670404 (1997-09-01), Dai
patent: 6252284 (2001-06-01), Muller et al.
patent: 6391695 (2002-05-01), Yu
patent: 6391782 (2002-05-01), Yu
patent: 6413802 (2002-07-01), Hu et al.
patent: 6451708 (2002-09-01), Ha
patent: 6514828 (2003-02-01), Ahn et al.
patent: 6759712 (2004-07-01), Bhattacharyya
patent: 2002/0155689 (2002-10-01), Ahn et al.
patent: 2003/0215988 (2003-11-01), Zahurak et al.
patent: 2004/0038461 (2004-02-01), Lee et al.
S. Wolf, Silicon Processing for the VLSI Era, vol. 2, p. 193.
Huang et al. “Sub-50 nm P-Channel FinFET,” IEEE Transactions on Electron Devices, vol. 48, No. 5, May 2001, pp. 880-886.
Yang et al. “35nm CMOS FinFETs,” 2002 Symposium on VLSI Technology Digest of Technical Papers, 2002, pp. 104-105.
Wong, “Beyond the Conventional Transistor,” IBM J. Res. & Dev., vol. 46, No. 2/3, Mar./May 2002, pp. 133-168.
Chau et al. “Advanced Depleted-Substrate Transistors: Single-gate, Double-gate and Tri-gate”, Extended Abstracts of the 2002 International Conference on Solid State Devices and Materials, Nagoya, Japan, 2002, pp. 68-69.
Yang et al. “25nm CMOS Omega FETs,” International Electron Devices Meeting (IEDM), Digest of Technical Papers, Dec. 2002, pp. 255-258.
Colinge et al. “Silicon-on-Insulator ‘Gate-All-Around Device’ ”, International Electron Devices Meeting (IEDM), Digest of Technical Papers, Dec. 1990, pp. 595-598.
Leobandung et al. “Wire-channel and wrap-around-gate metal-oxide-semiconductor field-effect transistors with a significant reduction of short channel effects”, J. Vac. Sci. Technology B, vol. 15, No. 6, Nov./Dec. 1997, American Vacuum Society, pp. 2791-2794.
Hu Chenming
Tseng Horng-Huei
Yang Fu-Liang
Yeo Yee-Chia
Fourson George
Haynes and Boone LLP
Taiwan Semiconductor Manufacturing Company , Ltd.
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