Real-time adaptive SRAM array for high SEU immunity

Details Real-time adaptive SRAM array for high SEU immunity Real-time adaptive SRAM array for high SEU immunity

2007-10-16

2007-10-16

Nguyen, Tuan T. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Testing

C714S042000

Reexamination Certificate

active

11308215

ABSTRACT:
A system and method for automatically adjusting one or more electrical parameters in a memory device, e.g., SRAM arrays. The system and method implements an SRAM sensing sub-array for accelerated collection of fail rate data for use in determining the operating point for optimum tradeoff between single event upset immunity and performance of a primary SRAM array. The accelerated fail rate data is input to an algorithm implemented for setting the SEU sensitivity of a primary SRAM memory array to a predetermined fail rate in an ionizing particle environment. The predetermined fail rate is maintained on a real-time basis in order to provide immunity to SEU consistent with optimum performance.

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Soli, et al., “Proton-Sensitive Custom SRAM Detector”, IEEE Nuclear Science Symposium and Medical Imaging Conference, 1991, vol. 3, pp. 1541-1545.
Yang, et al., “Design of Sub-50 nm FinFET Based Low Power SRAMs”, Berkeley Mid-term report, pp. 1-5.
Yang, et al., “Design of FinFET based SRAMs”, UC Berkeley EE 241 Project, May 8, 2003.

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