Semiconductor integrated circuit pattern verification...

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

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C716S030000, C716S030000, C703S014000

Reexamination Certificate

active

11176181

ABSTRACT:
A semiconductor integrated circuit pattern verification method includes executing simulation to obtain a simulation pattern to be formed on a substrate on the basis of a semiconductor integrated circuit design pattern, comparing the simulation pattern and the design pattern that is required on the substrate to detect a first difference value, extracting error candidates at which the first difference value is not less than a first predetermined value, comparing pattern shapes at the error candidates to detect a second difference value, combining, into one group, patterns whose second difference values are not more than a second predetermined value, and extracting a predetermined number of patterns from each group and verifying error candidates of the extracted patterns.

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patent: 2004/0146788 (2004-07-01), Nojima et al.
patent: 2005/0153217 (2005-07-01), Izuha et al.
patent: 9-319067 (1997-12-01), None
patent: 2003-107664 (2003-04-01), None
patent: WO-99/14638 (1999-03-01), None
Newmark et al.; “Large Area Optical Proximity Correction Using Pattern Based Corrections”: SPIE, vol. 2322, pp. 374-386 (1994).
Izuha et al.; “Pattern Verification Method, Pattern Verification System, Mask Manufacturing Method and Semiconductor Device Manufacturing Method”; U.S. Appl. No. 11/012,494, filed Dec. 16, 2004.

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