Method and apparatus for reducing electrical interconnection...

Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Configuration or pattern of bonds

Reexamination Certificate

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C257S738000, C257S698000

Reexamination Certificate

active

10322308

ABSTRACT:
A method and apparatus is provided that pertains to resisting crack initiation and propagation in electrical interconnections between components and substrates in ball grid array microelectronic packages. A hybrid of dielectric defined and non-dielectric defined electrical interconnects reduces the potential for electrical interconnection failure without having to control the dielectric defined interconnect ratio of substrates. In addition selective orientation of the dielectric defined edge portion of the electrical interconnect away from the point where cracks initiate resists crack propagation and component failure.

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patent: 6740971 (2004-05-01), Brooks et al.
patent: 6982486 (2006-01-01), Brooks et al.
patent: 7078823 (2006-07-01), Thurgood
patent: 7102217 (2006-09-01), Thurgood
patent: 2004/0113285 (2004-06-01), Tay et al.
patent: 2004/0201111 (2004-10-01), Thurgood

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