Tristate buses

Details Tristate buses Tristate buses

2007-06-19

2007-06-19

Kerveros, James C (Department: 2138)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

Reexamination Certificate

active

10011257

ABSTRACT:
Circuitry for testing and implementing a distributed tristate bus, the circuitry being configured in the testing mode, when a first signal is supplied to a first enable input and a test enable signal is operative, the cascade circuitry outputs a cascade out signal to the cascade input via the cascade output, causing the second cascade circuitry to disable the enable input of the second tristate cell, thereby to reduce the possibility of contention of the data bus during scan testing.

REFERENCES:
patent: 6543018 (2003-04-01), Adusumilli et al.

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