Memory device and input signal control method of a memory...

Details Memory device and input signal control method of a memory... Memory device and input signal control method of a memory...

2007-10-09

2007-10-09

Lamarre, Guy (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

C714S724000, C714S730000

Reexamination Certificate

active

10975006

ABSTRACT:
A memory device and a method of controlling an input signal of the memory device. In the method of controlling an input signal according to test modes, it is determined whether the input signal is in a first test mode or a second test mode. If the memory device is in the first test mode, in response to a control signal, an input signal is received through input pins. In response to a mode signal, the input signal is separated into data and an address. The separated data and address is applied to the core of a memory device. If the memory device is in the second test mode, an input signal is received through input pins and inverting input pins. In response to a mode signal, an address is separated from the input signal received through the input pins and the data is separated from the input signal received through the inverting input pins. The separated data and address are applied to the core of a memory device.

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