Semiconductor device and method of manufacture thereof

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

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C438S591000, C438S592000

Reexamination Certificate

active

11005385

ABSTRACT:
A dielectric material layer is formed over a workpiece, a metal layer is formed over the dielectric material layer, and a semiconductive material layer is formed over the metal layer. The workpiece is heated, causing a top portion of the metal layer to interact with the semiconductive material layer and causing a bottom portion of the metal layer to diffuse into the dielectric material layer. The metal layer portion that interacts with the semiconductive material layer forms a silicide, and the diffused metal layer portion forms a high dielectric constant gate material having a graded concentration of the metal from the metal layer. At least the semiconductive material layer and the dielectric material layer are patterned to form a gate and a gate dielectric of a transistor device. A source region and a drain region are formed in the workpiece proximate the gate and gate dielectric.

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patent: 2004/0014306 (2004-01-01), Komatsu
patent: 2004/0214400 (2004-10-01), Muraoka et al.
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“Front End Processes,” International Technology Roadmap for Semiconductor (ITRS), 2002 Update, pp. 45-62, http://member.itrs.net/.
“Front End Processes,” International Technology Roadmap for Semiconductor (ITRS), 2002 Edition, pp. 23-25, http://member.itrs.net/.
Kim, H., et al., “Nano-Scale Zirconia and Hafnia Dielectrics Grown by Atomic Layer Deposition: Crystallinity, Interface Structures and Electrical Properties,” ERC Teleseminar, May 6, 2004, pp. 1, 22-26.
Murarka, S.P., “Silicides for VLSI Applications,” 1983, pp. 30, 67-68, Academic Press, New York, NY, US.

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