Method of making strained semiconductor transistors having...

Details Method of making strained semiconductor transistors having... Method of making strained semiconductor transistors having...

2007-11-06

2007-11-06

Nguyen, Thanh (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S153000, C438S154000, C257SE21001

Reexamination Certificate

active

11081271

ABSTRACT:
A p-type field effect transistor (PFET) and an n-type field effect transistor (NFET) of an integrated circuit are provided. A first strain is applied to the channel region of the PFET but not the NFET via a lattice-mismatched semiconductor layer such as silicon germanium disposed in source and drain regions of only the PFET and not of the NFET. A process of making the PFET and NFET is provided. Trenches are etched in the areas to become the source and drain regions of the PFET and a lattice-mismatched silicon germanium layer is grown epitaxially therein to apply a strain to the channel region of the PFET adjacent thereto. A layer of silicon can be grown over the silicon germanium layer and a salicide formed from the layer of silicon to provide low-resistance source and drain regions.

REFERENCES:
patent: 6228722 (2001-05-01), Lu
patent: 6417547 (2002-07-01), Kang
patent: 2004/0262683 (2004-12-01), Bohr et al.

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