Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2007-11-27
2007-11-27
Chaudhari, Chandra (Department: 2891)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S596000, C257SE21682
Reexamination Certificate
active
11160269
ABSTRACT:
A method of fabricating a flash memory device is disclosed wherein, electrode spacers are formed on sides of self-aligned floating gates having a negative slope. Thus, upon etching of a stack gate after an interlayer dielectric film and a control gate are formed, a stringer of a control gate, which is formed by the negative slope of the self-aligned floating gates, can be prevented. Furthermore, because an isotropic etch process is used to remove element isolation films between the floating gates, the element isolation films do not remain on the sides of the floating gates. It is thus possible to prevent loss of the coupling ratio. Accordingly, failure of devices can be reduced and decreasing the program speed can be prevented.
REFERENCES:
patent: 6159801 (2000-12-01), Hsieh et al.
patent: 6403421 (2002-06-01), Ikeda et al.
patent: 2001-3086 (2001-01-01), None
Chaudhari Chandra
Hynix / Semiconductor Inc.
Marshall & Gerstein & Borun LLP
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