Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2007-10-30
2007-10-30
Britt, Cynthia (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S738000, C714S736000, C714S718000
Reexamination Certificate
active
10403817
ABSTRACT:
A test apparatus according to the present invention includes: a plurality of test modules, connected to either of the plurality of devices under test, for supplying a test signal to the connected device under test; a plurality of control apparatuses for controlling the plurality of test modules, and for testing the plurality of devices under test in parallel; and a connection switching section for switching topology of the plurality of control apparatuses and the plurality of test modules so that the plurality of control apparatuses connect with the plurality of devices under test respectively.
REFERENCES:
patent: 4989129 (1991-01-01), Arita et al.
patent: 5425036 (1995-06-01), Liu et al.
patent: 5675544 (1997-10-01), Hashimoto
patent: 5742840 (1998-04-01), Hansen et al.
patent: 5931953 (1999-08-01), Lesmeister
patent: 5991907 (1999-11-01), Stroud et al.
patent: 6028439 (2000-02-01), Arkin et al.
patent: 6077304 (2000-06-01), Kasuya
patent: 6108806 (2000-08-01), Abramovici et al.
patent: 6202182 (2001-03-01), Abramovici et al.
patent: 6631487 (2003-10-01), Abramovici et al.
patent: 6754868 (2004-06-01), Bristow et al.
patent: 2001/0016922 (2001-08-01), Takasugi et al.
patent: 2002/0038203 (2002-03-01), Tsuchiya
patent: 2002/0140451 (2002-10-01), Sakayori et al.
patent: 2003/0005375 (2003-01-01), Takasugi et al.
patent: 2003/0115519 (2003-06-01), Kwon et al.
patent: 2004/0143811 (2004-07-01), Kaelicke et al.
patent: 3-128473 (1991-05-01), None
patent: 2583055 (1996-11-01), None
patent: 2583056 (1996-11-01), None
patent: 2583057 (1996-11-01), None
patent: 2587940 (1996-12-01), None
patent: 2587941 (1996-12-01), None
patent: 2627751 (1997-04-01), None
patent: 63-298178 (1998-12-01), None
patent: 2000-163456 (2000-06-01), None
patent: 2000-267881 (2000-09-01), None
patent: 2001-506367 (2001-05-01), None
patent: 2001-320386 (2001-11-01), None
patent: 2001-522049 (2001-11-01), None
patent: 2002-141414 (2002-05-01), None
Patent Abstracts of Japan, Publication No. 03-128473, Publication Date: May 31, 1991, 2 pages.
Japanese Office Action for Japanese Application No. 2005-504180 mailed on Aug. 30, 2005, 2 pages.
International Search Report dated Jun. 29, 2004 (1 page).
Patent Abstracts of Japan; Publication No. 03-128473 dated May 31, 1991 (2 pages).
Patent Abstracts of Japan; Publication No. 63-298178 dated Dec. 5, 1988 (2 pages).
U.S. Office Action mailed May 15, 2006 issued in corresponding U.S. Appl. No. 10/813,594.
Office Action issued by the European Patent Office dated Nov. 21, 2006 in European Application No. 04723013.1-2216, PCT/JP2004004046, 3 pages.
U.S. Office Action issued in U.S. Appl. No. 10/404,002 mailed on Apr. 9, 2007, 16 pages.
Explanation of Circumstances Relating To Accelerated Examination submitted in Japanese Application No. 2004-380598 dated Mar. 1, 2007 and English translation thereof, 8 pages.
European Search Report issued in European Application No. EP 06 07 7162 dated Feb. 23, 2007, 6 pages.
Xia J. Q. et al.: “Dynamic Test Emulation for EDA-Based Mixed-Signal Test Development Automation” Proceedings of The International Test Conference (ITC). Washington, Oct. 21-25, 1995, New York, IEEE, US, 761-770, XP000552879 ISBN: 0-7803-2992-9.
Castelnuovo A. et al.: “Emulation-Based Design Errors Identification” Defect and Fault Tolerence in VLSI Systems, 2002. DFT 2002. Proceedings, 17th IEEE International Symposium on Nov. 6-8, 2002, Piscataway, NJ, USA, IEEE, Nov. 6, 2002 (Nov. 6, 2002), pp. 365-371, XP010625026 ISBN: 0-7695-1831-1.
Japanese Office Action “Notification of Reasons for Rejection” issued in Japanese Application No. 2004-380598 mailed on Apr. 3, 2007 and English translation thereof, 7 pages.
Dearborn, W. R., Perkins, E. G., Wong, J. J., Rolince, D., “The Virtual Test Program (V Test)”, 1998 IEEE Autotestcon Proceedings, IEEE Systems Readiness Technology Conference, 1998 IEEE, U.S.A. IEEE, Aug. 27, 1998, Catalog No. 98CH36179, pp. 149-159.
Advantest Corporation
Britt Cynthia
Gandhi Dipakkumar
Osha & Liang LLP
LandOfFree
Test apparatus and test method for testing plurality of... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Test apparatus and test method for testing plurality of..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Test apparatus and test method for testing plurality of... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3822320