Selective polysilicon stud growth

Details Selective polysilicon stud growth Selective polysilicon stud growth

2007-11-13

2007-11-13

Trinh, Michael (Department: 2822)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S256000, C438S264000, C438S399000, C438S488000

Reexamination Certificate

active

11041357

ABSTRACT:
A memory cell having a bit line contact is provided. The memory cell may be a 6F2memory cell. The bit line contact may have a contact hole bounded by insulating sidewalls, and the contact hole may be partially or completely filled with a doped polysilicon plug. The doped polysilicon plug may have an upper plug surface profile that is substantially free of concavities or substantially convex. Similarly, a storage node contact may comprise a doped polysilicon plug having an upper plug surface profile that is substantially free of concavities or that is substantially convex. Additionally, a semiconductor device having a conductive contact comprising a polysilicon plug may is provided. The plug may contact a capacitor structure.

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