Non-planar flash memory having shielding between floating gates

Details Non-planar flash memory having shielding between floating gates Non-planar flash memory having shielding between floating gates

2007-01-16

2007-01-16

Elms, Richard (Department: 2824)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S316000

Reexamination Certificate

active

10910191

ABSTRACT:
A first plurality of memory cells is formed on pillars in a first column of the array. A second plurality of memory cells is formed in a first set of trenches in the same column. The second plurality of memory cells is coupled to the first plurality of memory cells through a series connection of their source/drain regions. A second set of trenches, perpendicular to the first set, is formed to separate columns of the array. Wordlines are formed along rows of the array. The wordlines are formed into the second set of trenches in order to shield adjacent floating gates. Metal shields are formed in the first set of trenches along the rows and between floating gates on the pillars.

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