Method for setting design margin for LSI

Details Method for setting design margin for LSI Method for setting design margin for LSI

2007-03-27

2007-03-27

Lin, Sun James (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

10868832

ABSTRACT:
After predicting a relationship between a design margin set against a fabrication variation in design of an LSI and a yield, a specific design margin for attaining a given yield is calculated based on the predicated relationship. The yield is a delay yield obtained by cumulating a signal propagation delay time thereby achieving a probability that a signal propagated through a logic circuit of the LSI is delayed by a given amount of time, and the design margin is a derating factor indicating a ratio between the signal propagation delay time and a standard value of the signal propagation delay time.

REFERENCES:
patent: 5424985 (1995-06-01), McClure et al.
patent: 5627793 (1997-05-01), McClure
patent: 6235575 (2001-05-01), Kasai et al.
patent: 2003/0096492 (2003-05-01), Yamauchi

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