Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Reexamination Certificate
2007-01-09
2007-01-09
Phung, Anh (Department: 2824)
Static information storage and retrieval
Read/write circuit
Having particular data buffer or latch
C365S185030, C365S189040
Reexamination Certificate
active
11134435
ABSTRACT:
A data write circuit of a semiconductor storage device is provided in which a multi-bit write method can be employed even if data input takes a long time. The data write circuit includes a multi-bit decoder and data latch circuit for sequentially latching a plurality of data to be respectively written to a plurality of memory cells of multi-bits and are sequentially input in accordance with a change of an input multi-bit address, a column decoder for respectively applying latched data to sources of the memory cells based on a column address among the input address, and a cell drain voltage generator for simultaneously applying high cell drain voltage (approx. 5.0 volts) for writing data to the drains of the memory cells when all of the data are latched and are applied to the sources of the memory cells so as to respectively write the data to the memory cells.
REFERENCES:
patent: 5757700 (1998-05-01), Kobayashi
patent: 6243297 (2001-06-01), Nagatomo
patent: 7006397 (2006-02-01), Toda
patent: 2000-331486 (2000-11-01), None
Nguyen Dang
Oki Electric Industry Co. Ltd.
Studebaker Donald R.
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