Electrical computers and digital processing systems: support – Synchronization of clock or timing signals – data – or pulses
Reexamination Certificate
2007-07-10
2007-07-10
Perveen, Rehana (Department: 2116)
Electrical computers and digital processing systems: support
Synchronization of clock or timing signals, data, or pulses
Reexamination Certificate
active
10361620
ABSTRACT:
A semiconductor device that transmits data in wide bus width regardless of the width of an external data bus connected thereto. On the device's data output side, m-bit internal data is divided into n blocks. A data selection circuit selects m
pieces of data at a time and a data output section outputs these pieces of data to an external data bus of a width of L=m
bits. An output control circuit controls the selection of data by the data selection circuit and a synchronous signal output section outputs a synchronous signal indicative of selected data. A data input section accepts data transferred via an external data bus and a data get circuit outputs the data to an internal data bus corresponding to a synchronous signal a synchronous signal input section accepted. By getting data corresponding to all synchronous signals, the data get circuit will get m-bit data.
REFERENCES:
patent: 5289584 (1994-02-01), Thome et al.
patent: 5748917 (1998-05-01), Krein et al.
patent: 5896347 (1999-04-01), Tomita et al.
patent: 6754865 (2004-06-01), Haraguchi
Arent Fox LLP.
Chang Eric
Fujitsu Limited
Perveen Rehana
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