Method for reducing SRAM test time by applying power-up...

Details Method for reducing SRAM test time by applying power-up... Method for reducing SRAM test time by applying power-up...

2007-05-08

2007-05-08

Ton, David (Department: 2138)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

C714S719000

Reexamination Certificate

active

11063922

ABSTRACT:
Methods (400, 500, and600) are disclosed for testing a memory device by tailoring an algorithm (460) used in the testing based on the preferred or intrinsic data state425that is obtained upon power-up of an advanced technology SRAM memory device (100). The methods (400, 500, and600) take advantage of the observation that such SRAM devices repeatedly power-up in a preferred state310. Accordingly, one method500comprises powering-up510the memory device and reading520a preferred power-up data state of each cell of the memory device without memory initialization or writes. The method500then captures and stores530a data state associated with the preferred power-up data state of each cell100and utilizes the stored power-up data state310or an inverse of the power-up data state320to tailor540a test pattern used by the test algorithm460.

REFERENCES:
patent: 5289475 (1994-02-01), Slemmer
patent: 5983346 (1999-11-01), Wendell
patent: 6185138 (2001-02-01), Brady
patent: 6556479 (2003-04-01), Makuta et al.
patent: 6630838 (2003-10-01), Wong

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