Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
2007-09-11
2007-09-11
Britt, Cynthia (Department: 2138)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C714S746000, C714S799000, C714S727000, C714S729000, C714S797000, C713S300000, C713S310000, C713S320000, C713S324000
Reexamination Certificate
active
10674951
ABSTRACT:
An integrated circuit device includes at least one functional module which outputs save data in synchronism with a saving clock signal, a power supply control unit which selects one of the functional modules, and controls stop and resumption of power supply to the selected functional module, a save data storage unit which stores save data output from a functional module selected by the power supply control unit, and an error checking and correction unit which performs error checking and correction for the save data stored in the save data storage unit when the save data is to be restored to the functional module in synchronism with a restoration clock signal.
REFERENCES:
patent: 5502728 (1996-03-01), Smith, III
patent: 5701313 (1997-12-01), Purdham
patent: 5761489 (1998-06-01), Broseghini et al.
patent: 5784628 (1998-07-01), Reneris
patent: 6208170 (2001-03-01), Iwaki et al.
patent: 6212642 (2001-04-01), Seiler et al.
patent: 6493257 (2002-12-01), Coughlin et al.
patent: 6510528 (2003-01-01), Freeman et al.
patent: 6938175 (2005-08-01), Lee
patent: 2002/0162037 (2002-10-01), Wood et al.
patent: 2003/0188241 (2003-10-01), Zyuban et al.
patent: 5-108496 (1993-04-01), None
patent: 05-108496 (1993-04-01), None
patent: 06-052070 (1994-02-01), None
patent: 6-139153 (1994-05-01), None
patent: 06-139153 (1994-05-01), None
patent: 9-44277 (1997-02-01), None
patent: 10-78836 (1998-03-01), None
patent: 2000-82014 (2000-03-01), None
patent: 2000-163320 (2000-06-01), None
patent: 2001-350672 (2001-12-01), None
patent: 2002-182803 (2002-06-01), None
patent: 2002-196846 (2002-07-01), None
Kosonocky, S.V., et al., “Enhanced Multi-Threshold (MTCMOS) Circuits Using Variable Well Bias,”The International Symposium on Low Power Electronics and Design 2001, Huntington Beach, California, Aug. 6-7, 2001, pp. 165-169.
Shivakumar, P., et al., “Modeling the Effect of Technology Trends on the Soft Error Rate of Combinational Logic,”Proceedings of the International Conference on Dependable Systems and Networks, Washington, D.C., Jun. 23-26, 2002.
Arima Yukio
Ishibashi Koichiro
Yamashita Takahiro
Britt Cynthia
Christensen O'Connor Johnson & Kindness PLLC
Matsushita Electric - Industrial Co., Ltd.
Trimmings John P.
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