Fully depleted SOI MOSFET arrangement with sunken...

Details Fully depleted SOI MOSFET arrangement with sunken... Fully depleted SOI MOSFET arrangement with sunken...

2007-04-10

2007-04-10

Deo, Duy-Vu N. (Department: 1765)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

On insulating substrate or layer

C438S157000, C438S197000, C438S283000, C438S300000

Reexamination Certificate

active

10460402

ABSTRACT:
A fully depleted SOI MOSFET arrangement includes a buried oxide (BOX) layer with recesses in the BOX layer and a post extended upwardly between the recesses. A thin channel region is formed on the post and a gate over the channel. Deep source/drain region are adjacent to the channel region and extend into the recesses.

REFERENCES:
patent: 5164805 (1992-11-01), Lee
patent: 5273921 (1993-12-01), Neudeck et al.
patent: 5646058 (1997-07-01), Taur et al.
patent: 6350653 (2002-02-01), Adkisson et al.
patent: 6365465 (2002-04-01), Chan et al.
patent: 6483156 (2002-11-01), Adkisson et al.
patent: 6657261 (2003-12-01), Assaderaghi et al.
patent: 6677646 (2004-01-01), Ieong et al.
patent: 6717216 (2004-04-01), Baie et al.
patent: 6835981 (2004-12-01), Yamada et al.

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