Tester system having a multi-purpose memory

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Reexamination Certificate

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C324S765010

Reexamination Certificate

active

10435494

ABSTRACT:
An apparatus for testing an integrated circuit, the apparatus including a sequence control logic unit having an output channel connectable to a device under test, and a memory to store at least two types of data sets, each data set being used by the sequence control logic unit to determine a test pattern to output on the output channel.

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patent: 199 51 205 (2000-04-01), None
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“Reducing Test Application Time in High-level Test Generation” by Ravi et al. International Test Conference Proceedings, 2000 Publication Date: Oct. 3-5, 2000 pp. 829-838 INSPEC Accession No. 6859172.
International Search Report, International Application No. PCT/US03/14891, Sep. 18, 2003, pp. 1-2.

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