Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2007-04-24
2007-04-24
Soward, Ida M. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S314000, C257S315000, C257S327000, C257S336000, C257S344000, C257S347000, C257S348000, C257S349000, C257S350000, C257S351000, C257S352000, C257S353000, C257S354000, C257S521000, C257S527000, C257S627000, C257S628000, C257S900000
Reexamination Certificate
active
10839197
ABSTRACT:
A method of forming a raised source/drain proximate a spacer of a gate of a transistor on a substrate, and a semiconductor device of an integrated circuit employing the same. In one embodiment, the method includes orienting the gate substantially along a <100> direction of the substrate. The method also includes providing a semiconductor material adjacent the spacer of the gate to form a raised source/drain layer of the raised source/drain oriented substantially along a <100> direction of the substrate.
REFERENCES:
patent: 4998150 (1991-03-01), Rodder et al.
patent: 5023676 (1991-06-01), Tatsuta
patent: 5827774 (1998-10-01), Kitajima
patent: 5874341 (1999-02-01), Gardner et al.
patent: 5970330 (1999-10-01), Buynoski
patent: 6043936 (2000-03-01), Large
patent: 6137149 (2000-10-01), Kodama
patent: 6380088 (2002-04-01), Chan et al.
patent: 6506638 (2003-01-01), Yu
patent: 6506649 (2003-01-01), Fung et al.
patent: 6508693 (2003-01-01), Bouten
patent: 6646288 (2003-11-01), Yamazaki et al.
patent: 7049651 (2006-05-01), Mikolajick et al.
patent: 7064377 (2006-06-01), Hagemeyer et al.
patent: 2002/0063292 (2002-05-01), Armstrong et al.
patent: 2002/0127798 (2002-09-01), Prall
patent: 2003/0094674 (2003-05-01), Ipposhi et al.
patent: 2003/0209752 (2003-11-01), Cai et al.
patent: 2005/0093105 (2005-05-01), Yang et al.
Drowley, C.I., et al., “Model for Facet and Sidewall Defect Formation During Selective Epitaxial Growth of (001) Silicon,” Appl. Phys. Lett., Feb. 15, 1988, pp. 546-548, vol. 52, No. 7, American Institute of Physics.
Endo, N., et al., “Novel Device Isolation Technology with Selective Epitaxial Growth,” Transactions on Electron Devices, Sep. 1984, pp. 1283-1288, vol. ED-31, No. 9, IEEE.
Endo, N. et al., “Scaled CMOS Technology USING SEG Isolatioin and Buried Well Process,” IEEE Transactions on Electron Devices, Nov. 1986, pp. 1659-1666, vol. ED-33, No. 11, IEEE.
Ishitani, A., et al., “Facet Formation in Selective Silicon Epitaxial Growth,” Japanese Journal of Applied Physics, Oct. 1985, pp. 1267-1269, vol. 24, No. 10.
Ishitani, A., et al., “Silicon Selective Epitaxial Growth and Electrical Properties of Epi/Sidewall Interfaces,” Japanese Journal of Applied Physics, May 1989, pp. 841-848, vol. 28, No. 5.
Kitajima, H., et al., “Crystalline Defects in Selectively Epitaxial Silicon Layers,” Japanese Journal of Applied Physics, Dec. 1983, pp. L783-L785, vol. 22, No. 12.
Loo, R., et al., “Successful Selective Epitaxial Si1-xGexDeposition Process for HPT-BiCMOS and High Mobility Heterojunction pMOS Applications,” Journal of the Electrochemical Society, 2003, pp. G638-G647, vol. 150, No. 10, The Electromechanical Society, Inc.
Matsumoto, T., et al., “Novel SOI Wafer Engineering, Using Low Stress and High Mobility CMOSFET with <100> Channel for Embedding RF/Analog Applications,” IEDM 2002, pp. 663-666, IEEE.
Samavedam, S.B., et al., “Elevated Source Drain Devices Using Silicon Selective Epitaxial Growth,” J. Vac. Sci. Technol. B, May/Jun. 2000, pp. 1244-1250, vol. 18, No. 3, American Vacuum Society.
Sayama, H., et al., “Effect of <100> Channel Direction for High Performance SCE Immune pMOSFET with less than 0.15μm Gate Length,” IEDM Technical Digest, 1999, pp. 657-660, IEEE.
Slater & Matsil L.L.P.
Soward Ida M.
Taiwan Semiconductor Manufacturing Company , Ltd.
LandOfFree
Method of forming a raised source/drain and a semiconductor... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of forming a raised source/drain and a semiconductor..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of forming a raised source/drain and a semiconductor... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3760063