Methods of fabricating high voltage devices

Details Methods of fabricating high voltage devices Methods of fabricating high voltage devices

2007-04-24

2007-04-24

Tsai, H. Jey (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S210000, C438S224000, C257SE27050

Reexamination Certificate

active

11154431

ABSTRACT:
Methods of fabrication and devices include field plates formed during capacitor formation. Isolation structures are formed in a semiconductor substrate. Well regions are formed in the semiconductor substrate. Drain extension regions are formed in the well regions. A gate dielectric layer is formed over the device. A gate electrode layer is formed that serves as the gate electrode and a bottom capacitor plate. The gate electrode and the gate dielectric layer are patterned to form gate structures. Source and drain regions are formed within the well regions and the drain extension regions. A silicide blocking layer is formed that also serves as a capacitor dielectric. Field plates and a top capacitor plate are formed on the blocking layer.

REFERENCES:
patent: 4290077 (1981-09-01), Ronen
patent: 6168983 (2001-01-01), Rumennik et al.
patent: 6617652 (2003-09-01), Noda
patent: 6787437 (2004-09-01), Rumennik et al.
patent: 6797594 (2004-09-01), Hoshino et al.
patent: 6828631 (2004-12-01), Rumennik et al.
patent: 2003/0107081 (2003-06-01), Lee et al.
patent: 2003/0203512 (2003-10-01), Kweon

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