Semiconductor integrated circuit

Details Semiconductor integrated circuit Semiconductor integrated circuit

2007-07-24

2007-07-24

Lamarre, Guy (Department: 2138)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

C714S746000, C714S753000, C714S758000, C714S768000, C714S733000, C714S734000, C714S743000, C365S201000

Reexamination Certificate

active

10805227

ABSTRACT:
An ECC circuit has an error correction function of N (N is a natural number) bits for output data of a memory cell array. A BIST circuit reads background data out of test target addresses, and writes/reads inverted data of the background data in at least a part of the testing target addresses. An N+1 bit error detection circuit outputs a signal indicative of test NG (defective product) when a total of error bit numbers n1and n2detected by the ECC circuit during first and second readings exceeds N.

REFERENCES:
patent: 4680760 (1987-07-01), Giles et al.
patent: 5509132 (1996-04-01), Matsuda et al.
patent: 6910169 (2005-06-01), Sharma
C. L. Chen, et al., “Error-Correcting Codes for Semiconductor Memory Applications: A State-of-the-Art Review”, IBM J. Res. Develop, vol. 28, No. 2, Mar. 1984, pp. 124-134.

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