Read port circuit for register file

Static information storage and retrieval – Read/write circuit – Precharge

Reexamination Certificate

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C365S230050

Reexamination Certificate

active

11208911

ABSTRACT:
In one embodiment, a read port circuit includes a precharge circuit configured to precharge a first node in the read port circuit and a pulldown circuit coupled to the first node. The pulldown circuit is configured to conditionally discharge the first node responsive to a first plurality of wordline signals and a first plurality of data signals. Each of the wordline signals corresponds to a respective memory cell of a first plurality of memory cells, and each of the data signals corresponds to a respective memory cell and represents data stored in the respective memory cell. In some embodiments, the read port circuit may be included in a register file in an integrated circuit that also includes logic circuitry configured to generate an address for a read port.

REFERENCES:
patent: 5299158 (1994-03-01), Mason et al.
patent: 5894432 (1999-04-01), Lotfi
patent: 5923608 (1999-07-01), Payne
patent: 6038274 (2000-03-01), Ribeiro Filho et al.
patent: 6343348 (2002-01-01), Tremblay et al.
patent: 6542423 (2003-04-01), Kalyanasundharam et al.
patent: 6782521 (2004-08-01), Iadonato et al.
patent: 2006/0083074 (2006-04-01), Cottier et al.
Copy of U.S. Application Serial No. 11/208,912, filed Aug. 22, 05, 33 pages.

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